CMPBRANCH_INSTRS=0, DEBUG_INSTRS=0, BITFIELD_INSTRS=0, BITCOUNT_INSTRS=0, COPROC_INSTRS=000, DIVIDE_INSTRS=0
Instruction Set Attributes Register 0
BITCOUNT_INSTRS | Indicates the supported Bit Counting instructions 0 (0): None supported, ARMv7-M reserved 1 (1): Adds support for the CLZ instruction |
BITFIELD_INSTRS | Indicates the supported BitField instructions 0 (0): None supported, ARMv7-M reserved 1 (1): Adds support for the BFC, BFI, SBFX, and UBFX instructions |
CMPBRANCH_INSTRS | Indicates the supported combined Compare and Branch instructions 0 (0): None supported, ARMv7-M reserved 1 (1): Adds support for the CBNZ and CBZ instructions |
COPROC_INSTRS | Indicates the supported Coprocessor instructions 0 (000): None supported, except for separately attributed architectures, for example the Floating-point extension 1 (001): Adds support for generic CDP, LDC, MCR, MRC, and STC instructions 2 (010): As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions 3 (011): As for 2, and adds support for generic MCRR and MRRC instructions 4 (100): As for 3, and adds support for generic MCRR2 and MRRC2 instructions |
DEBUG_INSTRS | Indicates the supported Debug instructions 0 (0): None supported, ARMv7-M reserved 1 (1): Adds support for the BKPT instruction |
DIVIDE_INSTRS | Indicates the supported Divide instructions 0 (0): None supported, ARMv7-M reserved 1 (1): Adds support for the SDIV and UDIV instructions |